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Anyone rebuilt the PLL in an NEO-AES with the daughterboard?
This daughterboard was retrofitted in the first generation AES consoles (not the very first ones though), its purpose was to fix the Composite Video out by adjusting the main clock (24.167829 MHz).
I have an AES AEC here which has troubles with the PLL daughterboard, sync is off for RGB, not for Composite video though.
Was thinking about building up a simple clock divider first, then maybe re-implement the PLL circuit to get Composite Video back, haven't found any references to someone doing that to a AES yet.
https://wiki.neogeodev.org/index.php?title=Video_PLL
submitted by /u/maki9000
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Neo geo AES PLL Video daughterboard replacement
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