Now that all the technical hurdles have been overcome, it's time to have a look at what parts are going to be needed.
Since it's very easy to make a mistake during the design phase I usually go for a prototype design first, this means a design where mistakes can be more easily corrected by using THT chips so I can use sockets and don't have to desolder ROMs/GALs/CPLDS every time an error is found.
7.1) ROM size needed
Here I simply calculate the total space needed for one version of each game for each separate bus:
- main CPU (16 bit): 8960kB
- tiles (3 * 8 bit): 11712kB
- sprites (16 bit): 32896kB
- sound (8 bit): 10496kB
I've included Pontoon even if it's not emulated yet, you never know, the multi can come handy to someone who owns the actual Pontoon cabinet and is either missing the S18 boardset or have a faulty one. Worst case scenario we have some extra space in case a new undumped game is found.
Grand total is ~64MB, no way I can use good old EPROMs for that (I would need a trillion) so instead I chose to use flash, they are available in much bigger size than the biggest EPROMs ever produced. Drawback is higher capacity ones are only 3.3V which would require adding level shifters to the design (not like some chinese multis ).
7.2) Added storage technology constraints
Of course now design needs level shifters, a lot. And also a voltage regulator to convert the +5V coming from the S18 motherboard to 3.3V used by the chips on the multi. Here I didn't even think long, I chose a 3.3V 1A LDO regulator, typical consumption of the flash used is 15mA in read mode, plus the level shifters, plus the CPLD (RE of the custom chip), still there's plenty of slack here.
Also to reduce numbers of chips I'm using 16 bit flash even for 8 bit busses so need a couple of DEMUX.
7.3) The usual things
One decoupling capacitor per chip, one main filtering capacitor on the +5V rail, no dipbank this time but a coded switch, header for a remote dipbank/coded switch, pull-down resistors, connectors to attach to the mainboard, a JTAG connector for the CPLD and the CPLD of course (replaces the dozens of GALs I used during my first tests when working on the custom chip reproduction). And indeed sockets for all the chips.
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System 18 multi - 7) Consolidating the design
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